Wimol San-Um, Banlue Srisuchinwong, and Sawasd Tantaratana

pp. 165 - 180

Abstract

A low-power low-error single-ended virtually-grounded-drain class AB switched-current memory cell is presented. The proposed circuit is relatively simple, based on a basic class AB SI memory cell and a levelshifted grounded-gate amplifier. No large differential circuitry and complicated clocking schemes are required. All charge-injection, clock-feedthrough and conduction errors are reduced. As a design example using 0.5-µm CMOS technology, the power consumption is 120 µW at the bias current of 25 µA and supply
voltage of 2V. The optimal sampling frequency is at 45MHz. The SNR, SDR and SFDR are 59.7 dB, 61 dB and 73 dB, respectively. The total harmonic distortion is less than 0.4%. The transmission gain error and the DC
offset current error are less than 0.025 and 0.75 µA, respectively. Demonstrations of a forward difference integrator and comparisons to other approaches are also presented.